In the case of electronic equipment, the widely used conventional power supply voltage of 5 V used widely is reduced to 3.3 V or 2.5 V in order to reduce the IC (integrated circuit) power consumption, and situations which require the provision of an interface between different ICs which use different operating voltages with respect to signal level are increasing. For example, in the case of a system equipped with a PCI bus, while an IC on the core side uses 3.3 V, an IC on the expansion board side may use 3.3 V or 5 V. In such a case, a level shifting circuit is used that allows the core side to receive a signal at the voltage level of 3.3 V regardless of whether the voltage level of a signal from the expansion board side to the core side is 3.3 V or 5 V.
A conventional level shifting circuit equipped with this type of function is shown in FIG. 11. Said level shifting circuit uses N-channel MOS transistor (referred to as an “NMOS transistor” hereinafter) 100 as a transfer gate transistor. The drain terminal of NMOS transistor 100 is connected at port A to a digital IC (not shown) provided on the sender side, the source terminal is connected at port B to a digital IC (not shown) provided on the receiver side, and its gate terminal is connected to node s0 of bias circuit 102. Bias circuit 102 comprises diode 104 and resistor 106 connected in series between terminal C of power supply voltage VCC and ground, and it supplies fixed voltage VCC−VF at node s0, of diode 104 and resistor 106 to the gate of NMOS transistor 100 as bias voltage Vg. Here, VF represents the forward voltage drop of diode 104.
For example, to obtain a high level of 3.3 V at port B when a high level of 5 V is input to port A when the receiver side IC uses a 3.3 V system, assuming that the threshold voltage of NMOS transistor 100 is Vtn, bias voltage Vg should be set so that Vg−Vtn=3.3 V. That is, in general, the receiver side IC is a capacitive load when seen from port B, so that the source voltage (potential at port B) is restricted to level (Vg−Vtn), that is, the level obtained when gate voltage Vg has been reduced by threshold voltage Vtn, at NMOS transistor 100 regardless of the drain voltage (potential at port A), and the on-state in the saturation region is stabilized at said level. Therefore, to obtain an H level of 3.3 V at port B when power supply voltage VCC is 5 V and threshold voltage Vtn of NMOS transistor 100 is 0.9 V, bias voltage Vg should be set to 4.2 V, and 0.8 V should be selected for forward voltage drop VF of diode 104. Because the NMOS transistor turns on in the linear region and outputs the drain-source voltage when the high level of 3.3 V is input from the sender side IC, an H level of 3.3 V appears at port B. In addition, the same holds true when a signal input to port A is at the low level (normally 0 V), and a low level of 0 V appears at port B.
In the case of said level shifting circuit, the signal propagation delay time can be reduced to a value very close to zero by reducing the on-resistance of NMOS transistor 100, so that the level of the signal supplied from sender side IC, whether it is 3.3 V or 5 V, can be received by the receiver side IC as a single 3.3 V signal level instantaneously.
However, the level shifting circuit has the following shortcomings or restrictions.
(1) The level can be shifted only to a level lower than bias voltage Vg by threshold voltage Vtn of NMOS transistor 100, which is less than power supply voltage VCC. Thus, as described above, in order for the receiver side IC or the system which operates at the power supply voltage of 3.3 V to be able to receive signals from a 5 V system as well as a 3.3 V system, power supply voltage VCC of 5 V must be prepared, or the conventional level shifting circuit cannot be used.
(2) If the on-resistance were to be reduced so as to reduce the signal propagation delay time, NMOS transistor 100 would increase in size, and a large parasitic capacitance would be added between the gate and source or gate and drain. Said parasitic capacitance temporarily increases the gate potential through capacitive coupling to cause an overshoot of the output voltage when the input signal changes from low level to high level, so that accurate level shifting is hindered.
(3) Because a steady DC current flows through bias circuit 102, the power consumption is high. In particular, if the resistance value of resistor 106 is reduced to restrain the overshoot caused by the transition from low level to high level, the power consumption is further increased despite the fact that the restraining effect is small.
The present invention was conceived in light of the problems of the prior art, and its purpose is to present a level shifting circuit capable of quickly, reliably, and precisely shifting the level of an arbitrary input signal that is higher than the power supply voltage to an output signal level controlled by the power supply voltage.
Another purpose of the present invention is to present a low power level shifting circuit in which the DC current consumption is reduced.